With the progress in fabricating process of semiconductors in recent years, there has been a great reduction in the dimensions of MOSFETs used in LSI chips, in which a CMOSFET (Complementary Metal Oxide Semiconductor Field-Effect Transistor) is a circuit element. The voltage that can be applied to a MOSFET also is continuing to be reduced. Further, owing to requests for improved performance and increasing demand for various portable electronic devices and progress that has been made in batteries and peripherals other than the LSIs that construct these devices, and because of social demand for conservation of device operating power, which is related to the demand for better performance, and conservation of resources necessary when producing these devices, there is increasing demand for a reduction in the power-supply voltage and signal input/output amplitude of these devices.
As power-supply voltage and input/output signal amplitude, especially input signal amplitude, are reduced, there is increasing demand for a ratio of input signal amplitude to power-supply voltage that will allow an electronic circuit constituting an electronic device to operate normally. For example, in both an Nch-type MOSFET and Pch-type MOSFET, there is a limitation upon the effective voltage range of input voltage in enhancement-type FETs, which are used heavily in ordinary CMOSLSI chips. In an enhancement-type FET, there exists a threshold-value voltage that is unsupportable as an effective input voltage for the purpose of holding output current in the OFF state. If the input voltage applied to the gate is equal to or greater than a threshold-value voltage with respect to the source voltage in an Nch-type MOSFET or if it is less than a value obtained by subtracting the threshold-value voltage from the source voltage in a Pch-type MOSFET, then the input voltage is not supportable as an effective input voltage. The reason for this is that the MOSFET turns off if the gate-to-source voltage (or the absolute value thereof) is smaller than the threshold-value voltage (or the absolute value thereof).
Owing to lowering of power-supply voltage and a reduction in input signal amplitude, the ratio of the threshold-value voltage of a FET to the input voltage range increases, i.e., the ratio of the range of the input voltage that cannot be received as the effective input voltage increases, and the performance of the electronic circuitry essentially declines. Accordingly, there is growing demand for application of circuit techniques to enlarge a range supportable as effective input voltages in a MOSFET, for example, without being aware of the presence of the threshold-value voltage. A circuit known in the prior art obtains the final output signal by combining a differential amplifier having, e.g., an Nch-type MOSFET as the input section and a differential amplifier having a Pch-type MOSFET as the input section, and combining the output signals of the differential amplifier circuits. FIG. 7 is a diagram illustrating an example of the configuration of a typical differential amplifier circuit.
The circuit shown in FIG. 7 has a plus (non-inverting) input terminal IP, a minus (inverting) input terminal IM and an output terminal O. The operation of the terminals is as illustrated in FIG. 2, which shows the symbol of an ordinary differential-input and single-output type differential amplifier circuit. If we let VP, VM and VO represent input voltage to the non-inverting input terminal IP, input voltage to the inverting input terminal IM and output voltage from the output terminal O, respectively, the relationship among these is given by Equation (1) below.VO=A×(VP−VM)  (1)
Here A represents an amplification factor of a differential-input and single-output type differential amplifier.
In the circuit of FIG. 7, IC and ID represent equivalent constant-current sources, M33 to M38 represent Pch-type MOSFETs, M31, M32 and M39 to M42 represent Nch-type MOSFETs, and VB1 to VB3 represent bias-voltage sources.
The relationship among VP, VM and VO in the circuit of FIG. 7 is obtained as set forth below.
Let VDD represent power-source voltage, and let I31 to I34 represent the drain currents of the MOSFETs M31 to M34. For the sake of simplicity, let β(beta)x, Wx, Lx, Vthx, VDSx and VAx represent the gain coefficient β(beta), gate width, gate length, threshold-value voltage, drain-to-source voltage and Early voltage, respectively, of MOSFET Mx (where x is 31 to 34). If it is assumed that these MOSFETs are all operating in the saturation region, the relationships between the drain currents I31 to I34 and the input voltages VP, VM are given by Equations (2) to (5) below.
                              I          ⁢                                          ⁢          31                =                                                                              β                  31                                2                            ·                                                W                  31                                                  L                  31                                            ·                                                (                                      VP                    -                                          Vth                      31                                                        )                                2                                      ⁢                          (                              1                +                                                      VDS                    31                                                        VA                    31                                                              )                                ∝          VP                                    (        2        )                                          I          ⁢                                          ⁢          32                =                                                                              β                  32                                2                            ·                                                W                  32                                                  L                  32                                            ·                                                (                                      VM                    -                                          Vth                      32                                                        )                                2                                      ⁢                          (                              1                +                                                      VDS                    32                                                        VA                    32                                                              )                                ∝          VM                                    (        3        )                                          I          ⁢                                          ⁢          33                =                                                                              β                  33                                2                            ·                                                W                  33                                                  L                  33                                            ·                                                (                                      VDD                    -                    VP                    +                                          Vth                      33                                                        )                                2                                      ⁢                          (                              1                +                                                      VDS                    33                                                        VA                    33                                                              )                                ⁢                      ∝                          -              1                                ⁢          VP                                    (        4        )                                          I          ⁢                                          ⁢          34                =                                                                              β                  34                                2                            ·                                                W                  34                                                  L                  34                                            ·                                                (                                      VDD                    -                    VM                    +                                          Vth                      34                                                        )                                2                                      ⁢                          (                              1                +                                                      VDS                    34                                                        VA                    34                                                              )                                ⁢                      ∝                          -              1                                ⁢          VM                                    (        5        )            
The MOSFETs M35 and M36 essentially operate as equivalent constant-current sources supplied with respective bias voltages. If we let I35 and I36 represent the drain currents of MOSFETs M35 and M36, respectively, then Equations (6) and (7) below are obtained.I35−I31=I41−I33  (6)I36−I32=I42−I34  (7)
The output voltage VO in the output circuit constituted by MOSFETs M36, M38, M40 and M42 is proportional to the difference current between drain current I38 of MOSFET M38 and drain current I40 of MOSFET M40 and is represented by Equation (8) below.VO∝(I38−I40)  (8)
Equation (9) below is derived from Equations (2) to (5) using Equations (6), (7), the fact that the drain currents I35 and I36 of MOSFETS M35 and M36 are equal and the fact that drain currents I41 and I42 of MOSFET M41 and M42 are also equal because it is considered desirable for the MOSFETs M41 and M42 to be operating as current mirror circuits in which the gate width/gate length ratio is 1.
                                                                                          I                  ⁢                                                                          ⁢                  38                                -                                  I                  ⁢                                                                          ⁢                  40                                            =                                                I                  ⁢                                                                          ⁢                  36                                -                                  I                  ⁢                                                                          ⁢                  32                                -                                  (                                                            I                      ⁢                                                                                          ⁢                      42                                        -                                          I                      ⁢                                                                                          ⁢                      34                                                        )                                                                                                        =                                                I                  ⁢                                                                          ⁢                  36                                -                                  I                  ⁢                                                                          ⁢                  42                                -                                  I                  ⁢                                                                          ⁢                  32                                +                                  I                  ⁢                                                                          ⁢                  34                                                                                                        =                                                I                  ⁢                                                                          ⁢                  35                                -                                  I                  ⁢                                                                          ⁢                  41                                -                                  I                  ⁢                                                                          ⁢                  32                                +                                  I                  ⁢                                                                          ⁢                  34                                                                                                        =                                                                    I                    ⁢                                                                                  ⁢                    31                                    -                                      I                    ⁢                                                                                  ⁢                    33                                    -                                      (                                                                  I                        ⁢                                                                                                  ⁢                        32                                            -                                              I                        ⁢                                                                                                  ⁢                        34                                                              )                                                  ∝                                  (                                      VP                    -                    VM                                    )                                                                                        (        9        )            
Accordingly, Equation (10) below is obtained from Equation (8) above.VO∝(VP−VM)  (10)
In view of the foregoing, it will be understood that the circuit of FIG. 7 operates as a differential amplifier circuit overall.
Reference is had to Patent Document 1, which describes a rail-to-rail amplifier having an extended range of common-mode input voltages. FIG. 25 in Patent Document 1 discloses a differential amplifier circuit in which currents that flow in a load-element pair (diode-connected P-channel MOS transistors Mp15 and Mp17) of a first differential pair comprising N-channel MOS transistors (Mn11 and Mn12) are reflected by a current mirror and flow in a load-element pair (Mn14 and Mn15) of a second differential pair comprising P-channel MOS transistors (Mp11 and Mp12).
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-150427 (FIG. 25)
[Non-Patent Document 1]
Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill Higher Education, 2000, p. 326
I have now discovered that the entire disclosure of Patent Document 1 and Non-Patent Document 1 are incorporated herein by reference thereto.
In the differential amplifier circuit shown in FIG. 7, it is difficult to extend the range of the input voltage, output voltage and operating currents of the circuitry. This is derived from Equations (6), (7) indicating the operating requirements of the circuit.
For example, if the drain currents I31 and I32 of MOSFETs M31 and M32 do not fall within the following limits:I31<I35  (11)I32<I36  (12)then the output circuit constituted by the MOSFETs M35 to M42 will no longer operate normally.
This limitation is mitigated if the drain current I35 of MOSFET M35 or the drain current I36 of MOSFET M36 can be made sufficiently large. In this case, however, power-supply current consumption of the overall circuit increases.
In order for the MOSFETs M37 to M40 to operate normally, it is required that the current values
                                                                                          M                  ⁢                                                                          ⁢                  37                                :                                                      I                    ⁢                                                                                  ⁢                    35                                    -                                      I                    ⁢                                                                                  ⁢                    31                                                                                                                                            M                  ⁢                                                                          ⁢                  38                                :                                                      I                    ⁢                                                                                  ⁢                    36                                    -                                      I                    ⁢                                                                                  ⁢                    32                                                                                                                                            M                  ⁢                                                                          ⁢                  39                                :                                                      I                    ⁢                                                                                  ⁢                    41                                    -                                      I                    ⁢                                                                                  ⁢                    33                                                                                                                                            M                  ⁢                                                                          ⁢                  40                                :                                                      I                    ⁢                                                                                  ⁢                    42                                    -                                      I                    ⁢                                                                                  ⁢                    34                                                                                      }                            (        13        )            with regard to respective ones of these MOSFETs fall within limits decided by the relationship between bias voltages VB2 and VB3 being applied to the MOSFETs M37 to M40.
Furthermore, if it is attempted to extend the range of the output voltage VO too much, there is the possibility that the drain-to-source voltage of the MOSFETs M38, M40 will decline and that there will be a departure from the normal operating range decided by the relations of Equation (13).
Thus, it is evident that if at least one of the MOSFETs M37 to M40 does not operate normally, the overall differential amplifier circuit will cease operating normally.
The reason why it is difficult to extend the range of the input voltage, output voltage and operating currents of the circuitry in the differential amplifier circuit shown in FIG. 7 is that subtractive combination of separately generated currents is performed in the combining of the output current of the differential amplifier circuit having Nch-type MOSFETs M31 and M32 as an input stage and the output current of the differential amplifier circuit having Pch-type MOSFETs M33 and M34 as an input stage. Another reason is that MOSFETs separate from the differential amplifier circuit are inserted directly in the paths of these current signals.